The high power consumption of analog-to-digital converters (ADCs) with high resolution is a bottleneck in the high data rate communication system. 1-bit ADC system is considered to be a key communication system resolving the issue. Recently, 1-bit ADC system with time-oversampling has been studied as a spotlight technology because the additional information leads to increase in the achievable rate. A variety of studies have been done to enhance the data rate of the system with 1-bit ADC and time-oversampling. On one side, there are several papers treating the channel estimation issues based on the Bussgang theorem. However, their performances inevitably face the saturation in high signal-to-noise ratio (SNR) region. To overcome the limit, this paper provides the channel estimator which works well even in high SNR. We design the pilot sequence and maximum likelihood estimator to evaluate channel phase which is a critical parameter in 1-bit ADC system. By taking account for the distribution of gain in flat Rayleigh fading channel indirectly, our estimator behaves without need of channel gain information which is hard to get due to the nonlinearity of 1-bit ADC. The proposed estimator performs without error floor.