A 3.125-to-28.125 Gb/s Multi-Standard Transceiver with a Fully Channel-independent Operation in 40nm CMOS

Abstract

This paper presents a 3.125 Gb/s to 28.125 Gb/s multi-standard channel-independent parallel transceiver. The proposed clock and data recovery (CDR) IC achieves wide tuning range with low clock jitter because a ring oscillator in each channel is injection-locked to an LC VCO in a global clock generator. Each CDR lane generates a channel-independent injection clock signal using a variable clock divider and a highly linear phase rotator. In addition, a frequency tracking loop using a natural frequency detector is proposed to align the frequency of an injection-locked oscillator to the input data rate to suppress a periodic spur under injection. The test chip fabricated in 40nm CMOS achieves a power efficiency of 4.72 mW/Gb/s while generating integrated jitter of 976 ps(rms).