DC Field | Value | Language |
---|---|---|
dc.contributor.author | Seo, Jaewoo | ko |
dc.contributor.author | Jung, Jinwook | ko |
dc.contributor.author | Shin, Youngsoo | ko |
dc.date.accessioned | 2020-06-25T02:21:11Z | - |
dc.date.available | 2020-06-25T02:21:11Z | - |
dc.date.created | 2020-06-11 | - |
dc.date.issued | 2018-03 | - |
dc.identifier.citation | Conference on Design-Process-Technology Co-Optimization for Manufacturability XII | - |
dc.identifier.issn | 0277-786X | - |
dc.identifier.uri | http://hdl.handle.net/10203/274871 | - |
dc.description.abstract | Multi-bit flip-flops (MBFFs) are widely used in modern circuit designs because of their lower power consumption and smaller footprint. However, conventional MBFFs have routability issues due to the dense intra-cell connections. Since many horizontal connections are populated in the typical MBFF layouts, metal-2 (M2) tracks are highly occupied inside the cell. Accordingly, routers cannot leverage the M2 tracks for inter-cell connections. The conventional MBFFs also show a limited impact on the cell area reduction. Since the cell area saving of an MBFF mainly comes from the clock driver sharing, the layouts of other flip-flop modules remain almost the same. In this paper, we propose a compact MBFF with metal-less clock routing and smaller height implementation. To achieve a sparse population of M2 routing tracks, we vertically place MBFF modules and interconnect them using the poly layer. As a result, the wire length of M2 layer inside a cell is significantly reduced. We also propose the smaller cell height implementation for compact MBFF layouts. Assuming the default standard cell height of 9 tracks, we present a 6-track MBFF implementation and the glue logic which makes legal cell placement with the 9-track logic cells. Experiments with a few test circuits show that the number of routing grids having congestion overflow is reduced by 16% and 73%, on average, compared to the single-bit flip-flop and conventional MBFF based designs, respectively. Total cell area is also reduced by 8% and 2%, on average, compared to the single-bit flip-flop and conventional MBFF based designs, respectively. | - |
dc.language | English | - |
dc.publisher | SPIE-INT SOC OPTICAL ENGINEERING | - |
dc.title | A Compact Multi-Bit Flip-Flop with Smaller Height Implementation and Metal-Less Intra-Cell Routing | - |
dc.type | Conference | - |
dc.identifier.wosid | 000453761500008 | - |
dc.identifier.scopusid | 2-s2.0-85048402119 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | Conference on Design-Process-Technology Co-Optimization for Manufacturability XII | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | San Jose, CA | - |
dc.identifier.doi | 10.1117/12.2297519 | - |
dc.contributor.localauthor | Shin, Youngsoo | - |
dc.contributor.nonIdAuthor | Seo, Jaewoo | - |
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