Controller, semiconductor memory system and operating method thereof

Abstract

An operating method of a controller, comprising: <ul id="ul0001" list-style="none"> <li id="ul0001-0001" num="0000"></li> <ul id="ul0002" list-style="none"> <li id="ul0002-0001" num="0000"></li>generating, when a first ECC decoding operation to codeword read from a semiconductor memory device according to a hard read voltage fails, an optimization information corresponding the result of the first ECC decoding operation; generating one or more quantization intervals determined by the optimization information; and performing a second ECC decoding operation to codeword read from the semiconductor memory device according to soft read voltages determined by the quantization intervals and the hard read voltage, wherein the optimization information includes: deterioration information of a memory block; ECC decoder parameter information; and constituent code parameter information.