Characterizing the Worst-Case Wafer Delay in a Cluster Tool Operated in a K-Cyclic Schedule

Abstract

Cluster tools are widely used manufacturing equipment in semiconductor manufacturing systems and consist of several process chambers, loadlock modules, and a wafer transport robot. The operation of the cluster tool relies on decision making about the robot operations. Generally, a robot iteratively determines its next task according to a given task sequence. This tool schedule is called a cyclic schedule. If the same timing pattern repeats every K work cycles in a cyclic schedule, the schedule is called a K -cyclic schedule. In a cluster tool with a K -cyclic schedule, wafer delay, which is the time that a processed wafer is stored in the process chamber, becomes an important issue. In this study, we identify the worst-case wafer delay, which is the maximum value of wafer delay among all the K -cyclic schedules a cluster tool can have. To do this, we present timed event graph models for dual-armed and single-armed cluster tools and briefly explain the previous research on closed-form formulae of token delays in timed event graphs with K-cyclic schedules suggested by Lee et al. [1]. Finally, we propose a method for deriving a closed-form formula for the worst-case wafer delay in a cluster tool, which can be applied to arbitrary wafer flow patterns and time parameters.