High-Performance Field-Effect Transistor and Logic Gates Based on GaS-MoS(2 )van der Waals Heterostructure

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This work demonstrates a high-performance and hysteresis-free field-effect transistor based on two-dimensional (2D) semiconductors featuring a van der Waals heterostructure, MoS2 channel, and GaS gate insulator. The transistor exhibits a subthreshold swing of 63 mV/dec, an on/off ratio over 106 within a gate voltage of 0.4 V, and peak mobility of 83 cm2/(V s) at room temperature. The low-frequency noise characteristics were investigated and described by the Hooge mobility fluctuation model. The results suggest that the van der Waals heterostructure of 2D semiconductors can produce a high-performing interface without dangling bonds and defects caused by lattice mismatch. Furthermore, a logic inverter and a NAND gate are demonstrated, with an inverter voltage gain of 14.5, which is higher than previously reported by MoS2-based transistors with oxide dielectrics. Therefore, this transistor based on van der Waals heterostructure exhibits considerable potential in digital logic applications with low-power integrated circuits.
Publisher
American Chemical Society
Issue Date
2020-01
Language
English
Article Type
Article
Citation

ACS APPLIED MATERIALS & INTERFACES, v.12, no.4, pp.5106 - 5112

ISSN
1944-8244
DOI
https://doi.org/10.1021/acsami.9b20077
URI
http://hdl.handle.net/10203/272601
Appears in Collection
EE-Journal Papers(저널논문)
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