A 94-GHz Push-Push Frequency Doubler with Peak Total Power Efficiency of 16.28%

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dc.contributor.authorCHUNG, WOOHYUNko
dc.contributor.authorHong, Songcheolko
dc.date.accessioned2020-01-19T04:20:20Z-
dc.date.available2020-01-19T04:20:20Z-
dc.date.created2020-01-17-
dc.date.created2020-01-17-
dc.date.created2020-01-17-
dc.date.issued2019-08-28-
dc.identifier.citation2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)-
dc.identifier.urihttp://hdl.handle.net/10203/271470-
dc.description.abstractA highly efficient 94-GHz push-push frequency doubler is presented. The push-push frequency doubler is implemented with a commercial 65-nm CMOS process and can be operated in high-power mode (HPM) and high-efficiency mode (HEM). In HPM, it shows peak conversion gain of 1.94 dB, operating in the frequency range from 83.6 to 102.9 GHz (20.7%) with the input power of -1 dBm within 3-dB gain variation. Also at 94 GHz, it operates in the input power range of −11.9 to 8 dBm within 3-dB gain variation. In HEM, the peak total efficiency (P OUT /(P DC+ P IN )) is 16.28%, which is the highest among those of the reported W-Band frequency doublers.-
dc.languageEnglish-
dc.publisherIEEE-
dc.titleA 94-GHz Push-Push Frequency Doubler with Peak Total Power Efficiency of 16.28%-
dc.typeConference-
dc.identifier.wosid000528680700028-
dc.identifier.scopusid2-s2.0-85078019814-
dc.type.rimsCONF-
dc.citation.publicationname2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)-
dc.identifier.conferencecountryCC-
dc.identifier.conferencelocationHoliday Inn Nanjing Qinhuai South Suites, Nanjing-
dc.identifier.doi10.1109/RFIT.2019.8929163-
dc.contributor.localauthorHong, Songcheol-
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