A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 197
  • Download : 0
This brief presents an input-data-jitter-tolerant injection-type clock and data recovery (CDR) circuit with a super-harmonic injection-locked ring oscillator (SH-ILRO). Unlike prior injection-type CDRs that utilize a power-hungry CML-type data injection path or for which the data rate is limited to the process-defined CMOS logic bandwidth, the proposed injection-type CDR achieves energy-efficient data edge injection. The proposed wide-bandwidth source follower-based edge detector extracts the input data edge energy efficiently. The proposed SH-ILRO enables quarter-rate injection-locking without high-speed injection selection logic. Fabricated in 65-nm CMOS, the prototype injection-type CDR consumes 19.08 mW at 12 Gb/s with 87-MHz jitter transfer bandwidth and more than 1.0 UIpp jitter tolerance at 20 MHz.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2019-12
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.12, pp.1972 - 1976

ISSN
1549-7747
DOI
10.1109/TCSII.2019.2898647
URI
http://hdl.handle.net/10203/270952
Appears in Collection
EE-Journal Papers(저널논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0