A 45nm SOI-CMOS PLL with a wideband LC-VCO

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dc.contributor.authorLee, Kun-Seokko
dc.contributor.authorBeck, Sunghoko
dc.contributor.authorJeon, Hamheeko
dc.contributor.authorYoon, Youngchangko
dc.contributor.authorChoi, Jaehyoukko
dc.contributor.authorLee, Chang-Hoko
dc.contributor.authorKenney, J. Stevensonko
dc.date.accessioned2019-12-13T13:28:42Z-
dc.date.available2019-12-13T13:28:42Z-
dc.date.created2019-11-19-
dc.date.created2019-11-19-
dc.date.issued2011-11-01-
dc.identifier.citation54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011-
dc.identifier.urihttp://hdl.handle.net/10203/269704-
dc.description.abstractA 45nm SOI-CMOS PLL with a wideband LC-VCO is presented. The proposed PLL uses the advantage of SOI technology such as small parasitic capacitance and high Q-factor. The frequency range of the PLL is maximized because of a high maximum-to-minimum capacitance ratio of a capacitor bank. Measurement results show that the VCO generates 4.87-to-9.65GHz frequency signals with 65.8% frequency coverage. Fabricated chip occupies 0.09mm2 of active area and consumes less than 7mA current from single 1.0V supply.-
dc.languageEnglish-
dc.publisherIEEE-
dc.titleA 45nm SOI-CMOS PLL with a wideband LC-VCO-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.publicationname54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011-
dc.identifier.conferencecountryUS-
dc.identifier.conferencelocationYonsei University, Seoul-
dc.identifier.doi10.1109/MWSCAS.2011.6026273-
dc.contributor.localauthorChoi, Jaehyouk-
dc.contributor.nonIdAuthorLee, Kun-Seok-
dc.contributor.nonIdAuthorBeck, Sungho-
dc.contributor.nonIdAuthorJeon, Hamhee-
dc.contributor.nonIdAuthorYoon, Youngchang-
dc.contributor.nonIdAuthorLee, Chang-Ho-
dc.contributor.nonIdAuthorKenney, J. Stevenson-
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EE-Conference Papers(학술회의논문)
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