Area, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory

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dc.contributor.authorJin, Yko
dc.contributor.authorShihab, Mko
dc.contributor.authorJung, Myoungsooko
dc.date.accessioned2019-12-13T13:27:45Z-
dc.date.available2019-12-13T13:27:45Z-
dc.date.created2019-11-28-
dc.date.issued2014-06-14-
dc.identifier.citationMemoryForum-
dc.identifier.urihttp://hdl.handle.net/10203/269678-
dc.languageEnglish-
dc.publisherIEEE-
dc.titleArea, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.publicationnameMemoryForum-
dc.identifier.conferencecountryUS-
dc.identifier.conferencelocationMinneapolis, MN-
dc.contributor.localauthorJung, Myoungsoo-
dc.contributor.nonIdAuthorJin, Y-
dc.contributor.nonIdAuthorShihab, M-
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EE-Conference Papers(학술회의논문)
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