From High-Level Deep Neural Models to FPGAs
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Sharma, Hardik | ko |
| dc.contributor.author | PARK, JONGSE | ko |
| dc.contributor.author | Mahajan, Divya | ko |
| dc.contributor.author | Amaro, Emmanuel | ko |
| dc.contributor.author | Kim, Joon Kyung | ko |
| dc.contributor.author | Shao, Chenkai | ko |
| dc.contributor.author | Mishra, Asit | ko |
| dc.contributor.author | Esmaeilzadeh, Hadi | ko |
| dc.date.accessioned | 2019-12-13T13:26:20Z | - |
| dc.date.available | 2019-12-13T13:26:20Z | - |
| dc.date.created | 2019-12-04 | - |
| dc.date.issued | 2016-10-15 | - |
| dc.identifier.citation | International Symposium on Microarchitecture (MICRO) | - |
| dc.identifier.uri | http://hdl.handle.net/10203/269634 | - |
| dc.language | English | - |
| dc.publisher | IEEE and ACM SIGMICRO | - |
| dc.title | From High-Level Deep Neural Models to FPGAs | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | International Symposium on Microarchitecture (MICRO) | - |
| dc.identifier.conferencecountry | CH | - |
| dc.identifier.conferencelocation | Taipei, Taiwan | - |
| dc.contributor.nonIdAuthor | Sharma, Hardik | - |
| dc.contributor.nonIdAuthor | Mahajan, Divya | - |
| dc.contributor.nonIdAuthor | Amaro, Emmanuel | - |
| dc.contributor.nonIdAuthor | Kim, Joon Kyung | - |
| dc.contributor.nonIdAuthor | Shao, Chenkai | - |
| dc.contributor.nonIdAuthor | Mishra, Asit | - |
| dc.contributor.nonIdAuthor | Esmaeilzadeh, Hadi | - |
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