FlashGPU: Placing New Flash Next to GPU Cores

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dc.contributor.authorZhang, Jieko
dc.contributor.authorKwon, Miryeongko
dc.contributor.authorKim, Hyojongko
dc.contributor.authorKim, Hyesoonko
dc.contributor.authorJung, Myoungsooko
dc.date.accessioned2019-12-13T10:30:32Z-
dc.date.available2019-12-13T10:30:32Z-
dc.date.created2019-11-28-
dc.date.created2019-11-28-
dc.date.created2019-11-28-
dc.date.issued2019-06-
dc.identifier.citationThe 56th Design Automation Conference, (DAC), pp.1 - 6-
dc.identifier.urihttp://hdl.handle.net/10203/269403-
dc.description.abstractWe propose FlashGPU, a new GPU architecture that tightly blends new flash (Z-NAND) with massive GPU cores. Specifically, we replace global memory with Z-NAND that exhibits ultra-low latency. We also architect a flash core to manage request dispatches and address translations underneath L2 cache banks of GPU cores. While Z-NAND is a hundred times faster than conventional 3D-stacked flash, its latency is still longer than DRAM. To address this shortcoming, we propose a dynamic page-placement and buffer manager in Z-NAND subsystems by being aware of bulk and parallel memory access characteristics of GPU applications, thereby offering high-throughput and low-energy consumption behaviors.-
dc.languageEnglish-
dc.publisherACM-
dc.titleFlashGPU: Placing New Flash Next to GPU Cores-
dc.typeConference-
dc.identifier.wosid000482058200156-
dc.identifier.scopusid2-s2.0-85067831721-
dc.type.rimsCONF-
dc.citation.beginningpage1-
dc.citation.endingpage6-
dc.citation.publicationnameThe 56th Design Automation Conference, (DAC)-
dc.identifier.conferencecountryUS-
dc.identifier.conferencelocationLas Vegas Convention Center-
dc.identifier.doi10.1145/3316781.3317827-
dc.contributor.localauthorJung, Myoungsoo-
dc.contributor.nonIdAuthorZhang, Jie-
dc.contributor.nonIdAuthorKim, Hyojong-
dc.contributor.nonIdAuthorKim, Hyesoon-
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