Digitally Adaptive High-Fidelity Analog Array Signal Processing Resilient to Capacitive Multiplying DAC Inter-Stage Gain Error

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dc.contributor.authorJoshi, Siddharthko
dc.contributor.authorKim, Chulko
dc.contributor.authorThomas, Chris M.ko
dc.contributor.authorCauwenberghs, Gertko
dc.date.accessioned2019-12-13T07:23:45Z-
dc.date.available2019-12-13T07:23:45Z-
dc.date.created2019-11-15-
dc.date.created2019-11-15-
dc.date.issued2019-11-
dc.identifier.citationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.66, no.11, pp.4095 - 4107-
dc.identifier.issn1549-8328-
dc.identifier.urihttp://hdl.handle.net/10203/268888-
dc.description.abstractThis paper studies multi-stage capacitive mixed-signal matrix-vector multiplying digital-to-analog (MDAC) conversion topologies for highly energy-efficient, high-resolution, and high-dimensional MIMO analog processing systems. In order to mitigate nonlinearity due to radix errors and capacitive mismatch encountered in compact low-power MDAC realizations, we introduce stochastic successive approximation, or S(2)A, as an online optimization algorithm for adaptive array analog signal processing amenable to efficient implementation in massively parallel mixed-signal hardware. S(2)A offers a direct alternative to stochastic gradient descent overcoming several of its shortcomings, such as its sensitivity to model error, while improving on the rate and quality of convergence. S(2)A overcomes non-convergence typically encountered with gradient descent for non-convex optimization landscapes induced by a mismatch in capacitive multiplying digital-to-analog converter components when applied to adaptive analog signal processing. Experimental validation of S(2)A in mixed-signal hardware for real-time RF adaptive beamforming demonstrates 65 dB of over-the-air, multipath interferer suppression in fewer than 25 S(2)A iterations.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleDigitally Adaptive High-Fidelity Analog Array Signal Processing Resilient to Capacitive Multiplying DAC Inter-Stage Gain Error-
dc.typeArticle-
dc.identifier.wosid000494680200001-
dc.identifier.scopusid2-s2.0-85077448718-
dc.type.rimsART-
dc.citation.volume66-
dc.citation.issue11-
dc.citation.beginningpage4095-
dc.citation.endingpage4107-
dc.citation.publicationnameIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS-
dc.identifier.doi10.1109/TCSI.2019.2926447-
dc.contributor.localauthorKim, Chul-
dc.contributor.nonIdAuthorJoshi, Siddharth-
dc.contributor.nonIdAuthorThomas, Chris M.-
dc.contributor.nonIdAuthorCauwenberghs, Gert-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorSignal processing algorithms-
dc.subject.keywordAuthorArray signal processing-
dc.subject.keywordAuthorAdaptive arrays-
dc.subject.keywordAuthorCapacitors-
dc.subject.keywordAuthorAdaptive systems-
dc.subject.keywordAuthorOptimization-
dc.subject.keywordAuthorMultiplying digital-to-analog conversion (MDAC)-
dc.subject.keywordAuthormixed-signal matrix-vector multiplication (MVM)-
dc.subject.keywordAuthoranalog signal processing (ASP)-
dc.subject.keywordAuthormulti-input multi-output (MIMO)-
dc.subject.keywordAuthorleast-mean-squares (LMS) adaptive filtering-
dc.subject.keywordAuthornon-convex optimization-
dc.subject.keywordAuthorInternet-of-Things (IoT)-
dc.subject.keywordPlusCALIBRATION-
dc.subject.keywordPlusNETWORKS-
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