DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Geon-Beom | ko |
dc.contributor.author | Kim, Choong-Ki | ko |
dc.contributor.author | Yoo, Min-Soo | ko |
dc.contributor.author | Hur, Jae | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.date.accessioned | 2019-12-13T07:23:07Z | - |
dc.date.available | 2019-12-13T07:23:07Z | - |
dc.date.created | 2019-11-28 | - |
dc.date.created | 2019-11-28 | - |
dc.date.issued | 2019-11 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.66, no.12, pp.5126 - 5132 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | http://hdl.handle.net/10203/268879 | - |
dc.description.abstract | The gate-induced drain leakage (GIDL) current is one of the major leakage sources in a dynamic random-access memory (DRAM) cell transistor. In addition to band-to-band tunneling (BTBT), which causes GIDL in the gate-to-drain overlap region, the generation of interface traps in the gate dielectric increases the GIDL current by trap-assisted two-step tunneling (TATT). In this article, the influence of OFF-state stress on the generation of the interface traps, which deteriorates GIDL, was quantitatively analyzed with charge pumping (CP) characterization method in buried-channel array transistors (BCATs) for DRAM cells. The applied stress increased the GIDL current while simultaneously degrading device performance including such as transconductance ( $\text{g}_{\text {m}}$ ) and ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ), due to the generation of the interface traps. By using the CP characterization, the interface traps were spatially profiled along the gate-to-drain overlap region in the junction. Trap distribution inside the energy bandgap was also characterized. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Effect of Off-state Stress on Gate-Induced Drain Leakage by Interface Traps in Buried-Gate FETs | - |
dc.type | Article | - |
dc.identifier.wosid | 000502043000012 | - |
dc.identifier.scopusid | 2-s2.0-85076368896 | - |
dc.type.rims | ART | - |
dc.citation.volume | 66 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 5126 | - |
dc.citation.endingpage | 5132 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.identifier.doi | 10.1109/TED.2019.2947603 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Kim, Choong-Ki | - |
dc.contributor.nonIdAuthor | Yoo, Min-Soo | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Band-to-band tunneling (BTBT) | - |
dc.subject.keywordAuthor | buried-channel array transistor (BCAT) | - |
dc.subject.keywordAuthor | charge pumping (CP) | - |
dc.subject.keywordAuthor | dynamic random-access memory (DRAM) | - |
dc.subject.keywordAuthor | gate-induced drain leakage (GIDL) | - |
dc.subject.keywordAuthor | interface trap | - |
dc.subject.keywordAuthor | leakage current | - |
dc.subject.keywordAuthor | OFF-state stress | - |
dc.subject.keywordAuthor | trap-assisted two-step tunneling (TATT) | - |
dc.subject.keywordPlus | CELL TRANSISTOR | - |
dc.subject.keywordPlus | NEW-MODEL | - |
dc.subject.keywordPlus | CHARGE | - |
dc.subject.keywordPlus | MOS | - |
dc.subject.keywordPlus | DENSITY | - |
dc.subject.keywordPlus | DEGRADATION | - |
dc.subject.keywordPlus | RELIABILITY | - |
dc.subject.keywordPlus | PROFILES | - |
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