DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells

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As DRAM scaling becomes ever more difficult, Phase Change Memory (PCM) is attracting attention as a new memory or storage class memory. Unfortunately, PCM cell data can be changed by frequently writing ‘0’ to adjacent cells. This phenomenon is called Write Disturbance (WD). To mitigate WD errors with low performance overhead, we propose a Detection Cell PCM (DC-PCM). In the DC-PCM, additional cells called Detection Cells (DC) are allocated to a memory-line to pre-detect WD errors. For pre-detection, we propose schemes that give DCs higher WD-vulnerability than normal cells. However, additional time is needed to verify DCs. To hide the time needed to perform the verifications during a WRITE, DC-PCM enables the local word-lines of DCs to operate independently (Decoupled Word-line), and verifies different directions in parallel (Parallel DC-Verification). After verification, the DC-PCM increases the WD-vulnerability of the DCs, or restores the memory-line data (DC-Correction). In our simulation, DC-PCMs showed performance comparable to a WD-free PCM for all workloads.
Publisher
IEEE
Issue Date
2019-12
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON COMPUTERS, v.68, no.12, pp.1741 - 1754

ISSN
0018-9340
DOI
10.1109/TC.2019.2930972
URI
http://hdl.handle.net/10203/268802
Appears in Collection
EE-Journal Papers(저널논문)
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