DC Field | Value | Language |
---|---|---|
dc.contributor.author | Seo, Min-Jae | ko |
dc.contributor.author | Kim, Ye Dam | ko |
dc.contributor.author | Chung, Jae-Hyun | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2019-11-22T02:20:15Z | - |
dc.date.available | 2019-11-22T02:20:15Z | - |
dc.date.created | 2019-11-22 | - |
dc.date.created | 2019-11-22 | - |
dc.date.created | 2019-11-22 | - |
dc.date.created | 2019-11-22 | - |
dc.date.issued | 2019-06-11 | - |
dc.identifier.citation | 39th Symposium on VLSI Technology / 33rd Symposium on VLSI Circuits, pp.C72 - C73 | - |
dc.identifier.uri | http://hdl.handle.net/10203/268521 | - |
dc.description.abstract | This work proposes a dual-residue pipelined-SAR ADC, that generates two residue signals from a single amplifier, which eliminates the need for gain-matching calibration. A capacitive interpolating SAR conversion technique is also proposed for the second stage for power efficiency. A prototype ADC fabricated in a 40nm CMOS occupies an active area of 0.026 mm(2) and achieves an SNDR of 62.1 dB at Nyquist and 67.1 dB SFDR under a 0.9 V supply. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.title | A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC | - |
dc.type | Conference | - |
dc.identifier.wosid | 000531736500024 | - |
dc.identifier.scopusid | 2-s2.0-85073914809 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | C72 | - |
dc.citation.endingpage | C73 | - |
dc.citation.publicationname | 39th Symposium on VLSI Technology / 33rd Symposium on VLSI Circuits | - |
dc.identifier.conferencecountry | JA | - |
dc.identifier.conferencelocation | Rihga Royal Hotel Kyoto | - |
dc.identifier.doi | 10.23919/VLSIC.2019.8778005 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
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