DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shin, Hyein | ko |
dc.contributor.author | Sim, Jaehyeong | ko |
dc.contributor.author | Lee, Daewoong | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2019-11-21T08:20:14Z | - |
dc.date.available | 2019-11-21T08:20:14Z | - |
dc.date.created | 2019-08-19 | - |
dc.date.created | 2019-08-19 | - |
dc.date.created | 2019-08-19 | - |
dc.date.created | 2019-08-19 | - |
dc.date.created | 2019-08-19 | - |
dc.date.issued | 2019-11-06 | - |
dc.identifier.citation | 2019 ACM/IEEE International Conference On Computer Aided Design | - |
dc.identifier.uri | http://hdl.handle.net/10203/268510 | - |
dc.description.abstract | Deep neural networks (DNNs) are widely used for real-world applications. However, large amount of kernel and intermediate data incur a memory wall problem in resource-limited edge devices. The recent advances of a binary deep neural network (BNN) and a computing inmemory (CIM) have effectively alleviated this bottleneck especially when they are combined together. However, previous CIM-based accelerators for BNN are highly vulnerable to process/supply voltage/temperature (PVT) variation, resulting in severe accuracy degradation which makes them impractical to be employed in real-world edge devices. To address this vulnerability, we propose a PVT-robust accelerator architecture for BNN with a computable 4T embedded DRAM (eDRAM) cell array. First, we implement the XNOR operation of BNN in a time-multiplexed manner by utilizing the fundamental read operation of the conventional eDRAM cell. Next, a PVT-robust bit-count based on charge sharing is proposed with a computable 4T eDRAM cell array. In result, the proposed architecture achieves 6.9× less variation in PVT-variant environments which guarantees a stable accuracy and 2.03-49.4× improvement of energy efficiency over previous CIM-based accelerators. | - |
dc.language | English | - |
dc.publisher | IEEE/ACM | - |
dc.title | A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks | - |
dc.type | Conference | - |
dc.identifier.wosid | 000524676400032 | - |
dc.identifier.scopusid | 2-s2.0-85077788939 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | 2019 ACM/IEEE International Conference On Computer Aided Design | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | The Westin Westminster | - |
dc.identifier.doi | 10.1109/ICCAD45719.2019.8942072 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
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