DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Myoungjun | ko |
dc.contributor.author | Kim, Soontae | ko |
dc.date.accessioned | 2019-11-11T06:21:09Z | - |
dc.date.available | 2019-11-11T06:21:09Z | - |
dc.date.created | 2019-11-11 | - |
dc.date.issued | 2019-10 | - |
dc.identifier.citation | JOURNAL OF SUPERCOMPUTING, v.75, no.10, pp.6746 - 6776 | - |
dc.identifier.issn | 0920-8542 | - |
dc.identifier.uri | http://hdl.handle.net/10203/268336 | - |
dc.description.abstract | In embedded systems such as automotive systems, multi-core processors are expected to improve performance and reduce manufacturing cost by integrating multiple functions on a single chip. However, inter-core interference in shared last-level cache (LLC) results in increased and unpredictable execution times for time-sensitive tasks (TSTs), which have (soft) timing constraints, thereby increasing the deadline miss rates of such systems. In this paper, we propose a time-sensitivity-aware dead block-based shared LLC architecture to mitigate these problems. First, a time-sensitivity indication bit is added to each cache block, which allows the proposed LLC architecture to be aware of instructions/data belonging to TSTs. Second, portions of the LLC space are allocated to general tasks without interfering with TSTs by developing a time-sensitivity-aware dead block-based cache partitioning technique. Third, to reduce the deadline miss rate of TSTs further, we propose a task matching in shared caches and a cache partitioning scheme that considers the memory access characteristics and the time-sensitivity of tasks (TATS). The TATS is combined with our proposed dead block-based scheme. Our evaluation shows that the proposed schemes reduce deadline miss rates of TSTs compared to conventional shared caches. On a dual-core system, compared to a baseline, equal partitioning, and state-of-the-art quality-of-service-aware cache partitioning, our proposed dead block-based cache partitioning provides 9.3%, 30.5%, and 2.6% lower average deadline miss rates, respectively. On a quad-core system, compared to the baseline, equal partitioning, and state-of-the-art quality-of-service-aware cache partitioning, the combination of our proposed schemes provides 21.2%, 17.7%, and 4.1% lower average deadline miss rates, respectively. | - |
dc.language | English | - |
dc.publisher | SPRINGER | - |
dc.title | Time-sensitivity-aware shared cache architecture for multi-core embedded systems | - |
dc.type | Article | - |
dc.identifier.wosid | 000492960000022 | - |
dc.identifier.scopusid | 2-s2.0-85066062019 | - |
dc.type.rims | ART | - |
dc.citation.volume | 75 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 6746 | - |
dc.citation.endingpage | 6776 | - |
dc.citation.publicationname | JOURNAL OF SUPERCOMPUTING | - |
dc.identifier.doi | 10.1007/s11227-019-02891-w | - |
dc.contributor.localauthor | Kim, Soontae | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Multi-core | - |
dc.subject.keywordAuthor | Shared caches | - |
dc.subject.keywordAuthor | Quality of service | - |
dc.subject.keywordAuthor | Cache partitioning | - |
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