DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cho, WJ | ko |
dc.contributor.author | Ahn, CG | ko |
dc.contributor.author | Im, KJ | ko |
dc.contributor.author | Yang, JH | ko |
dc.contributor.author | Oh, Jihun | ko |
dc.contributor.author | Baek, IB | ko |
dc.contributor.author | Lee, S | ko |
dc.date.accessioned | 2019-11-08T04:20:04Z | - |
dc.date.available | 2019-11-08T04:20:04Z | - |
dc.date.created | 2019-11-05 | - |
dc.date.issued | 2004-06 | - |
dc.identifier.citation | IEEE ELECTRON DEVICE LETTERS, v.25, no.6, pp.366 - 368 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10203/268264 | - |
dc.description.abstract | A novel plasma-doping technique for fabricating nanoscale silicon-on-insulator (SOI) MOSFETs has been investigated. The source/drain (S/D) extensions of the tri-gate structure SOI n-MOSFETs were formed by using an elevated temperature plasma-doping method. Even though the activation annealing after plasma doping was excluded to minimize the diffusion of dopants, which resulted in a laterally abrupt S/D junction, we obtained a low sheet resistance of 920 Omega/rectangle by the elevated temperature plasma doping of 527 degreesC. A tri-gate structure silicon-on-insulator n-MOSFET with a gate length of 50 nm was successfully fabricated and revealed suppressed short-channel effects. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Fabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping technique | - |
dc.type | Article | - |
dc.identifier.wosid | 000221659700008 | - |
dc.identifier.scopusid | 2-s2.0-2942746700 | - |
dc.type.rims | ART | - |
dc.citation.volume | 25 | - |
dc.citation.issue | 6 | - |
dc.citation.beginningpage | 366 | - |
dc.citation.endingpage | 368 | - |
dc.citation.publicationname | IEEE ELECTRON DEVICE LETTERS | - |
dc.identifier.doi | 10.1109/LED.2004.829007 | - |
dc.contributor.localauthor | Oh, Jihun | - |
dc.contributor.nonIdAuthor | Cho, WJ | - |
dc.contributor.nonIdAuthor | Ahn, CG | - |
dc.contributor.nonIdAuthor | Im, KJ | - |
dc.contributor.nonIdAuthor | Yang, JH | - |
dc.contributor.nonIdAuthor | Baek, IB | - |
dc.contributor.nonIdAuthor | Lee, S | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | elevated temperature | - |
dc.subject.keywordAuthor | low damage | - |
dc.subject.keywordAuthor | MOSFETs | - |
dc.subject.keywordAuthor | nanoscale | - |
dc.subject.keywordAuthor | plasma doping | - |
dc.subject.keywordAuthor | silicon-on-insulator (SOI) | - |
dc.subject.keywordAuthor | tri-gate structure | - |
dc.subject.keywordPlus | CMOS | - |
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