Fabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping technique

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dc.contributor.authorCho, WJko
dc.contributor.authorAhn, CGko
dc.contributor.authorIm, KJko
dc.contributor.authorYang, JHko
dc.contributor.authorOh, Jihunko
dc.contributor.authorBaek, IBko
dc.contributor.authorLee, Sko
dc.date.accessioned2019-11-08T04:20:04Z-
dc.date.available2019-11-08T04:20:04Z-
dc.date.created2019-11-05-
dc.date.issued2004-06-
dc.identifier.citationIEEE ELECTRON DEVICE LETTERS, v.25, no.6, pp.366 - 368-
dc.identifier.issn0741-3106-
dc.identifier.urihttp://hdl.handle.net/10203/268264-
dc.description.abstractA novel plasma-doping technique for fabricating nanoscale silicon-on-insulator (SOI) MOSFETs has been investigated. The source/drain (S/D) extensions of the tri-gate structure SOI n-MOSFETs were formed by using an elevated temperature plasma-doping method. Even though the activation annealing after plasma doping was excluded to minimize the diffusion of dopants, which resulted in a laterally abrupt S/D junction, we obtained a low sheet resistance of 920 Omega/rectangle by the elevated temperature plasma doping of 527 degreesC. A tri-gate structure silicon-on-insulator n-MOSFET with a gate length of 50 nm was successfully fabricated and revealed suppressed short-channel effects.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleFabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping technique-
dc.typeArticle-
dc.identifier.wosid000221659700008-
dc.identifier.scopusid2-s2.0-2942746700-
dc.type.rimsART-
dc.citation.volume25-
dc.citation.issue6-
dc.citation.beginningpage366-
dc.citation.endingpage368-
dc.citation.publicationnameIEEE ELECTRON DEVICE LETTERS-
dc.identifier.doi10.1109/LED.2004.829007-
dc.contributor.localauthorOh, Jihun-
dc.contributor.nonIdAuthorCho, WJ-
dc.contributor.nonIdAuthorAhn, CG-
dc.contributor.nonIdAuthorIm, KJ-
dc.contributor.nonIdAuthorYang, JH-
dc.contributor.nonIdAuthorBaek, IB-
dc.contributor.nonIdAuthorLee, S-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorelevated temperature-
dc.subject.keywordAuthorlow damage-
dc.subject.keywordAuthorMOSFETs-
dc.subject.keywordAuthornanoscale-
dc.subject.keywordAuthorplasma doping-
dc.subject.keywordAuthorsilicon-on-insulator (SOI)-
dc.subject.keywordAuthortri-gate structure-
dc.subject.keywordPlusCMOS-
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