DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cho, WJ | ko |
dc.contributor.author | Yang, JH | ko |
dc.contributor.author | Im, K | ko |
dc.contributor.author | Oh, Jihun | ko |
dc.contributor.author | Lee, S | ko |
dc.contributor.author | Parr, K | ko |
dc.date.accessioned | 2019-11-08T03:20:06Z | - |
dc.date.available | 2019-11-08T03:20:06Z | - |
dc.date.created | 2019-11-05 | - |
dc.date.issued | 2003-11 | - |
dc.identifier.citation | JOURNAL OF THE KOREAN PHYSICAL SOCIETY, v.43, no.5, pp.892 - 897 | - |
dc.identifier.issn | 0374-4884 | - |
dc.identifier.uri | http://hdl.handle.net/10203/268262 | - |
dc.description.abstract | We have obtained systematic simulation and experimental results for 30-nm-gate-length metal-oxide-semiconductor field-effect transistor (MOSFET) fabricated on ultra-thin silicon-on-insulator (SOI) substrates. The two-dimensional process simulation and the device simulation were carried out to optimize the fabrication process conditions and the device characteristics of 30-nm-gate-length SOI MOSFETs. A new simple source/drain formation technique using the solid-phase diffusion (SPD) method was developed, Based on the simulation results and the SPD ultra-shallow junction formation technique, we successfully fabricated 30-nm-gate-length SOI nMOSFETs. The experimental results for the 30-nm-gate-length SOI nMOSFETs showed good transistor behaviors and superior device scalability. | - |
dc.language | English | - |
dc.publisher | KOREAN PHYSICAL SOC | - |
dc.title | Fabrication and process simulation of SOI MOSFETs with a 30-nm gate length | - |
dc.type | Article | - |
dc.identifier.wosid | 000186615200016 | - |
dc.identifier.scopusid | 2-s2.0-0344120148 | - |
dc.type.rims | ART | - |
dc.citation.volume | 43 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 892 | - |
dc.citation.endingpage | 897 | - |
dc.citation.publicationname | JOURNAL OF THE KOREAN PHYSICAL SOCIETY | - |
dc.contributor.localauthor | Oh, Jihun | - |
dc.contributor.nonIdAuthor | Cho, WJ | - |
dc.contributor.nonIdAuthor | Yang, JH | - |
dc.contributor.nonIdAuthor | Im, K | - |
dc.contributor.nonIdAuthor | Lee, S | - |
dc.contributor.nonIdAuthor | Parr, K | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | SOI | - |
dc.subject.keywordAuthor | nano-MOSFET | - |
dc.subject.keywordAuthor | SPD | - |
dc.subject.keywordAuthor | silumation | - |
dc.subject.keywordAuthor | 30 nm gate | - |
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