Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages

Cited 4 time in webofscience Cited 0 time in scopus
  • Hit : 284
  • Download : 0
DC FieldValueLanguage
dc.contributor.authorLee, Wonyoungko
dc.contributor.authorKang, Mincheolko
dc.contributor.authorHong, Seokinko
dc.contributor.authorKim, Soontaeko
dc.date.accessioned2019-09-17T06:20:39Z-
dc.date.available2019-09-17T06:20:39Z-
dc.date.created2019-09-17-
dc.date.issued2019-09-
dc.identifier.citationIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.27, no.9, pp.2033 - 2045-
dc.identifier.issn1063-8210-
dc.identifier.urihttp://hdl.handle.net/10203/267505-
dc.description.abstractDuring the past decade, the endurance of NAND flash memory has severely deteriorated. The maximum number of program and erase cycles has fallen significantly with emerging of multilevel cell (MLC) and triple-level cell (TLC) technology, and scaling down of the cell size. Wear leveling is a general solution used to alleviate this issue; it enables cells to wear down evenly but it cannot actually mitigate the wearing of the cells. Accordingly, techniques are required to minimize the actual cell degradation. This paper proposes endurance-enhancing lower state encoding. The key insight leveraged by the proposed technique is the data pattern-related characteristic of MLC and TLC NAND flash memories, in which the lower the state of the cells, the lower the occurrence of wear out. Thus, our proposed scheme encodes input data to make the cell state as low as possible in consideration of interpage relation. As a result, the wear out of the memory cells can be minimized and their lifetime is improved by 62.7% in a file type and 43.0% in MySQL. Experimental results indicate that our scheme shows better lifetime improvement than other schemes in most cases.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleInterpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages-
dc.typeArticle-
dc.identifier.wosid000483017700006-
dc.identifier.scopusid2-s2.0-85071377462-
dc.type.rimsART-
dc.citation.volume27-
dc.citation.issue9-
dc.citation.beginningpage2033-
dc.citation.endingpage2045-
dc.citation.publicationnameIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS-
dc.identifier.doi10.1109/TVLSI.2019.2912228-
dc.contributor.localauthorKim, Soontae-
dc.contributor.nonIdAuthorHong, Seokin-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorData storage systems-
dc.subject.keywordAuthorencoding-
dc.subject.keywordAuthorflash memories-
dc.subject.keywordAuthorreliability-
dc.subject.keywordPlusARCHITECTURE-
dc.subject.keywordPlusENHANCEMENT-
dc.subject.keywordPlusMITIGATION-
dc.subject.keywordPlusRETENTION-
dc.subject.keywordPlusLIFETIME-
dc.subject.keywordPlusSCHEME-
Appears in Collection
CS-Journal Papers(저널논문)
Files in This Item
There are no files associated with this item.
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 4 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0