(A) double down conversion mixer design for low power receiver

Abstract

This thesis presents a double down conversion (DDC) mixer for low power receiver. The proposed ar-chitecture is composed of series of two mixers. The $1^{st}$ mixer of single balanced structure (SBS) is not needed a circuit such as a balun, so that reduces the power consumption of a receiver. The $1^{st}$ mixer employs three techniques: current reuse transconductance (Gm) technique improves a voltage conversion gain (VCG), sup-pression LO-IF feedthrough using symmetric switching stage and RC filter, and common mode feedback (CMFB) circuit compensates output swing headroom. Due to current driven passive I/Q $2^{nd}$ mixer, the pro-posed DDC mixer achieves a high VCG. And by adopting the structure of series transistor switching stage and switching sequence technique, the $2^{nd}$ mixer operates same function as using 25% duty cycle I/Q LO signal which uses only 50% duty cycle I/Q LO signal without 25% duty cycle I/Q LO signal generation circuit. The proposed DDC mixer is designed and fabricated in 65nm technology. Simulation results show 13.7dB VCG, 32dB single side band noise figure (SSB-NF), -29dBm P1dB, and -13.6dBm IIP3 while consuming 33$\mu$W from 0.6V supply.