(An) ultra-low power logarithmic power detector

Abstract

This thesis presents two types of ultra-low power CMOS logarithmic power detectors with a 65nm CMOS process. Each proposed power detector consists of a rectifier and a logarithmic circuit. MOS transistors at both rectifiers all operate in the sub-threshold region. The logarithmic circuit of the first proposed power detector follows a conventional feedback type, and the second proposed power detector is implemented with a sub-threshold operating MOS transistor load, which is newly suggested in this thesis. The active areas of power detectors are $125 \mu m \times 40 \mu m$ and $60 \mu m \times 55 \mu m$. The proposed power detectors consume $8.11 \mu W and 0.2 \mu W$, respectively, under a 0.6V supply, and dynamic ranges are 41 dB and 21 dB, respectively, with $\pm$ 1 dB error at 915MHz.