Low-power wireline equalizer for high-speed serial link

Abstract

a power-efficient equalization techniques is proposed for a high data-rate multi-standard wireline re-ceiver. First, a low-frequency-equalizing continuous time linear equalizer (LFE-CTLE) compensates for not only the short-term inter-symbol interference (ISI) from high-frequency channel loss but also the long-term ISI from the low-frequency channel loss without additional power consumption compared to the previous CTLE. LFE-CTLE can reduce the required number of taps and power consumption of the following decision feedback equalizer (DFE). A 2-tap speculative DFE adopts 4-phase clocking techniques to reduce the number of summation nodes and latches for low-power consumption. The proposed receiver is designed in 65-nm LP CMOS technology with 1.-2V supply voltage. It can achieve 28-Gb/s data rate with a 24-mW power efficien-cy.