Planar packaging for grating-coupled silicon photonic chips using angle-polished silica waveguide blocks

Abstract

Silicon photonics is a powerful technology to fabricate photonic integrated circuits (PICs) for various applications because of its fabrication compatibility that permits the re-use of silicon-based electronics fabrication infrastructure and design techniques. Moreover, the high contrast of refractive index at telecommunication wavelength between silicon waveguide core and silica cladding permits ultracompact guided optical components while allowing more flexibilities in the photonic circuit layout. Diffraction grating-based coupling has been proposed not only to carry out the significant mode size difference between optical fibers and integrated nanophotonic waveguides, but also to support scalable optical interfaces from the surface-normal direction instead of edges of PIC. Despite its relaxed alignment tolerance which is an attractive advantage for economic packaging, the grating coupling is inherently a near-vertical coupling, so a vertical profile is generally produced instead of planar packaging. The non-planar structure is unpleasing because of its tendency to have poor mechanical durability and bulky size.

In this thesis, a novel planar fiber-to-chip coupling scheme for PICs is suggested. Efficient light coupling between a silicon-based PIC with diffraction grating-based couplers and a standard single-mode optical fiber oriented in parallel with the PIC chip is realized by utilizing an angle-polished silica waveguide block fabricated with well-established planar light circuit (PLC) fabrication processes. When compared to the angle-polished-fiber-based coupling technique, the demonstrated method can significantly decrease the distance between the fiber core and the grating coupler, and thereby offers a number of advantages in mechanical stability and misalignment tolerances. Our simulations as well as experimental results suggest that the proposed technique is applicable to the passive-alignment-based photonics packaging processes. In-plane and misalignment tolerance parallel to the PIC plane is found out to be more than 5 $\mu$m, and out-of-plane misalignment tolerance is better than 9 $\mu$m with about 1 dB excess loss.