Design of a supply-noise-insensitive PLL

Abstract

Phase-locked loop (PLL) is an essential building block in the digital communication system. Among them, ring voltage-controlled oscillator (RVCO) based PLLs are widely used in the integrated system due to its small occupied area and wide frequency tuning range. However, RVCO has high sensitivity to power supply voltage, the noise on power supply may degrade the overall jitter performance of the PLL. As CMOS process undergo large scale down in recent years, the nominal power supply has become lower. Therefore, power supply noise effect on frequency synthesizer has become significant. To suppress the supply noise, several techniques have been investigated in the past. Low-dropout(LDO) regulator is one of the general solutions to suppress the supply noise. However, it requires additional power and a large decoupling capacitor for stability. An alternative way would be to cancel the power supply noise effect on frequency synthesizer. Basically, ring oscillator has positive sensitivity to supply, total supply sensitivity will be reduced by adding compensation circuits which have negative sensitivity to supply. Such ways require low power consumption, robustness under PVT variation, small area.

In this thesis, the author proposes two types of supply-regulated PLL that remove the feedback loop in LDO: (1) a supply-noise-insensitive PLL using source-follower (SF) regulator and (2) a supply-noise-insensitive PLL using feed-forward amplifier-based supply regulator. Both types of PLL are implemented in 65\thinspace nm CMOS, a prototype PLLs at 3.2GHz achieve supply noise rejection of 30dB for a $10mV_pp$ supply noise around the loop bandwidth.