Atomic layer deposited metal gate stack for logic and memory devices

Abstract

Recently, 3D structures devices such as FinFETs and vertical NAND device have been actively adopted in logic and memory devices. The atomic layer deposition (ALD) process is necessary to realize the 3D structure devices. However, the properties of ALD metal electrode have not been extensively studied, especially for band-edge work function metal. In this dissertation, we investigated the properties of the metal gate stack prepared by ALD for logic and memory devices. The effective work function (eWF) of Al-doped titanium carbide (TiAlC) metal electrodes demonstrated using ALD method shows a strong dependency on the underlying gate dielectrics. The ALD TiAlC has a low work function on the $HfO_2$ dielectric regardless of the process conditions, indicating that an $ALD-TiAlC/HfO_2$ gate stack is a promising candidate for 3D nMOSFETs. The titanium nitride (TiN) deposition via ALD was also performed using titanium chloride for the PMOS applications. The ALD TiN has a high work the function regardless of dielectric materials, whereas its eWF is affected by upper low resistive metal. Additionally, the gate stacks using the formation of interface dipole were proposed to make the high work function of ALD TiN. In the 3D charge trap flash (CTF) device, the gate electrode is composed by chemical vapor deposition tungsten (CVD W) using WF6 source for a low resistance and ALD TiN for high work function metal. In this case, the memory device is inevitably degraded by fluorine diffusion along the grain boundaries of TiN. The CTF device with CVD W electrode shows that erase and retention properties are significantly affected by fluorine. In order to systematically study the effects of fluorine from the CVD W process, the mechanism of deterioration of the charge trap device was clarified and the memory reliability was analyzed.