(A) single LC VCO-based multi-standard ethernet transceiver IC supporting a fully channel-independent operation

Abstract

The ever-increasing data rate demands necessitate the emergence of new communication standards operating at higher data rates. Even though the clock and data recovery circuits have been proposed to support various data rate of Ethernet standards, these architectures cannot achieve a low clock jitter with a fully channel-independent operation. In this thesis, a single LC VCO-based transceiver IC to guarantee the low clock jitter with the fully channel-independent operation is proposed. In this architecture, the injection locked loop with a natural frequency detector and the improved clock path to achieve a better performance of the clock recovery are also proposed.