DC Field | Value | Language |
---|---|---|
dc.contributor.author | Roh, Dong-Hyun | ko |
dc.contributor.author | Lee, Tae-Gyung | ko |
dc.contributor.author | Lee, Tae-Eog | ko |
dc.date.accessioned | 2019-05-28T09:25:32Z | - |
dc.date.available | 2019-05-28T09:25:32Z | - |
dc.date.created | 2019-05-28 | - |
dc.date.issued | 2019-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.32, no.2, pp.236 - 249 | - |
dc.identifier.issn | 0894-6507 | - |
dc.identifier.uri | http://hdl.handle.net/10203/262228 | - |
dc.description.abstract | In a cluster tool for semiconductor manufacturing, a wafer waits within a chamber after processing until it is unloaded by the robot. Such wafer delays degrade wafer quality due to residual gases and heat, even cause quality failures. A cluster tool mostly operates in a K-cyclic schedule, where an identical timing pattern repeats for each K cycles, because of sporadic disruptions in process times or robot task times and the closed-architecture of the tool scheduler. In addition, it is hard to predict the K-cyclic schedule that the tool will reach. Such a K-cyclic schedule makes wafer delays at each chamber repeat K different values. Therefore, such variability of wafer delays increases the risk of quality failure. Therefore, we examine the maximum wafer delay among all possible K-cyclic schedules called the worst-case wafer delay in this paper. We first characterize the maximum cyclicity K of tool schedules. We then develop closed-form formulas for most frequently used wafer flow patterns and an optimization model that computes the worst-case wafer delay. We also identify factors that affect the worst-case wafer delay and their influences by experiments. Finally, we suggest tool operation guidelines for lowering the worst-case wafer delay. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | K-Cyclic Schedules and the Worst-Case Wafer Delay in a Dual-Armed Cluster Tool | - |
dc.type | Article | - |
dc.identifier.wosid | 000466924100012 | - |
dc.identifier.scopusid | 2-s2.0-85065399388 | - |
dc.type.rims | ART | - |
dc.citation.volume | 32 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 236 | - |
dc.citation.endingpage | 249 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | - |
dc.identifier.doi | 10.1109/TSM.2019.2910399 | - |
dc.contributor.localauthor | Lee, Tae-Eog | - |
dc.contributor.nonIdAuthor | Roh, Dong-Hyun | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Dual-armed cluster tool | - |
dc.subject.keywordAuthor | K-cyclic schedule | - |
dc.subject.keywordAuthor | worst-case wafer delay | - |
dc.subject.keywordAuthor | timed event graph | - |
dc.subject.keywordAuthor | quality variability | - |
dc.subject.keywordPlus | RESIDENCY TIME CONSTRAINTS | - |
dc.subject.keywordPlus | TRANSIENT PROCESSES | - |
dc.subject.keywordPlus | FEEDBACK-CONTROL | - |
dc.subject.keywordPlus | START-UP | - |
dc.subject.keywordPlus | SYSTEMS | - |
dc.subject.keywordPlus | SCHEDULABILITY | - |
dc.subject.keywordPlus | (MAX | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.