K-Cyclic Schedules and the Worst-Case Wafer Delay in a Dual-Armed Cluster Tool

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dc.contributor.authorRoh, Dong-Hyunko
dc.contributor.authorLee, Tae-Gyungko
dc.contributor.authorLee, Tae-Eogko
dc.date.accessioned2019-05-28T09:25:32Z-
dc.date.available2019-05-28T09:25:32Z-
dc.date.created2019-05-28-
dc.date.issued2019-05-
dc.identifier.citationIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.32, no.2, pp.236 - 249-
dc.identifier.issn0894-6507-
dc.identifier.urihttp://hdl.handle.net/10203/262228-
dc.description.abstractIn a cluster tool for semiconductor manufacturing, a wafer waits within a chamber after processing until it is unloaded by the robot. Such wafer delays degrade wafer quality due to residual gases and heat, even cause quality failures. A cluster tool mostly operates in a K-cyclic schedule, where an identical timing pattern repeats for each K cycles, because of sporadic disruptions in process times or robot task times and the closed-architecture of the tool scheduler. In addition, it is hard to predict the K-cyclic schedule that the tool will reach. Such a K-cyclic schedule makes wafer delays at each chamber repeat K different values. Therefore, such variability of wafer delays increases the risk of quality failure. Therefore, we examine the maximum wafer delay among all possible K-cyclic schedules called the worst-case wafer delay in this paper. We first characterize the maximum cyclicity K of tool schedules. We then develop closed-form formulas for most frequently used wafer flow patterns and an optimization model that computes the worst-case wafer delay. We also identify factors that affect the worst-case wafer delay and their influences by experiments. Finally, we suggest tool operation guidelines for lowering the worst-case wafer delay.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleK-Cyclic Schedules and the Worst-Case Wafer Delay in a Dual-Armed Cluster Tool-
dc.typeArticle-
dc.identifier.wosid000466924100012-
dc.identifier.scopusid2-s2.0-85065399388-
dc.type.rimsART-
dc.citation.volume32-
dc.citation.issue2-
dc.citation.beginningpage236-
dc.citation.endingpage249-
dc.citation.publicationnameIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING-
dc.identifier.doi10.1109/TSM.2019.2910399-
dc.contributor.localauthorLee, Tae-Eog-
dc.contributor.nonIdAuthorRoh, Dong-Hyun-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorDual-armed cluster tool-
dc.subject.keywordAuthorK-cyclic schedule-
dc.subject.keywordAuthorworst-case wafer delay-
dc.subject.keywordAuthortimed event graph-
dc.subject.keywordAuthorquality variability-
dc.subject.keywordPlusRESIDENCY TIME CONSTRAINTS-
dc.subject.keywordPlusTRANSIENT PROCESSES-
dc.subject.keywordPlusFEEDBACK-CONTROL-
dc.subject.keywordPlusSTART-UP-
dc.subject.keywordPlusSYSTEMS-
dc.subject.keywordPlusSCHEDULABILITY-
dc.subject.keywordPlus(MAX-
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