A novel mechanism for delay-insensitive data transfer based on current-mode multiple valued logic

Abstract

By conventional delay-insensitive data encodings, the number of required wires for transferring N-bit data is 2N+1. To reduce the required number of wires to N+1, and thus, reducing complexity in designing a large scaled chip, a novel data transfer mechanism based on current-mode multiple valued logic is proposed. Effectiveness of proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings at the 0.25-mum CMOS technology. Simulation results of 32-bit data transfer with 10 rum wire length demonstrate that proposed data transfer mechanism reduces the time-power product values of dual-rail and 1-of-4 encoding by 55.5% and 8.5%, respectively, in addition to the reduction of the number of wire by about half.