DC Field | Value | Language |
---|---|---|
dc.contributor.author | Oh, MH | ko |
dc.contributor.author | Har, Dongsoo | ko |
dc.date.accessioned | 2019-04-15T16:31:52Z | - |
dc.date.available | 2019-04-15T16:31:52Z | - |
dc.date.created | 2013-05-08 | - |
dc.date.issued | 2005-05 | - |
dc.identifier.citation | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E88A, pp.1379 - 1383 | - |
dc.identifier.issn | 0916-8508 | - |
dc.identifier.uri | http://hdl.handle.net/10203/255882 | - |
dc.description.abstract | Conventional delay-in sensitive (DI) data encodings require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, a DI data transfer mechanism based on current-mode multiple valued logic (CMMVL), where N-bit data transfer can be performed with only N+1 wires, is proposed. The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25-mu m CMOS technology. Simulation results with wire lengths of 4 mm or larger demonstrate that the CMMVL scheme significantly reduces delay-power product values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more. | - |
dc.language | English | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.subject | CIRCUITS | - |
dc.subject | DESIGN | - |
dc.title | Low delay-power product current-mode multiple valued logic for delay-insensitive data transfer mechanism | - |
dc.type | Article | - |
dc.identifier.wosid | 000229253400039 | - |
dc.identifier.scopusid | 2-s2.0-24144497775 | - |
dc.type.rims | ART | - |
dc.citation.volume | E88A | - |
dc.citation.beginningpage | 1379 | - |
dc.citation.endingpage | 1383 | - |
dc.citation.publicationname | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | - |
dc.identifier.doi | 10.1093/ietfec/e88-a.5.1379 | - |
dc.contributor.localauthor | Har, Dongsoo | - |
dc.contributor.nonIdAuthor | Oh, MH | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | delay-insensitive data transfer | - |
dc.subject.keywordAuthor | globally asynchronous locally synchronous system | - |
dc.subject.keywordAuthor | current-mode multiple valued logic | - |
dc.subject.keywordPlus | CIRCUITS | - |
dc.subject.keywordPlus | DESIGN | - |
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