Asynchronous multiple-issue on-chip bus with in-order/out-of-order completion

Abstract

A multiple-issue on-chip bus of a layered architecture in a Globally Asynchronous Locally Synchronous (GALS) design style, supporting in-order/out-of-order completion, is proposed in this letter. The throughput of the proposed on-chip bus is increased by 31.3% and 34.3%, while power consumption overhead is only 6.76% and 3.98%, respectively, as compared to an asynchronous single-issue on-chip bus.