Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Shin, In-Sup | ko |
| dc.contributor.author | Kim, Jae-Joon | ko |
| dc.contributor.author | Shin, Youngsoo | ko |
| dc.date.accessioned | 2019-04-15T16:14:20Z | - |
| dc.date.available | 2019-04-15T16:14:20Z | - |
| dc.date.created | 2014-11-26 | - |
| dc.date.created | 2014-11-26 | - |
| dc.date.issued | 2014-01 | - |
| dc.identifier.citation | Asia South Pacific Design Automation Conference, pp.179 - 184 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/255695 | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000350791700037 | - |
| dc.identifier.scopusid | 2-s2.0-84897848604 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 179 | - |
| dc.citation.endingpage | 184 | - |
| dc.citation.publicationname | Asia South Pacific Design Automation Conference | - |
| dc.identifier.conferencecountry | SI | - |
| dc.identifier.conferencelocation | Singapore | - |
| dc.contributor.localauthor | Shin, Youngsoo | - |
| dc.contributor.nonIdAuthor | Kim, Jae-Joon | - |
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