Self-Repairing Digital System With Unified Recovery Process Inspired by Endocrine Cellular Communication

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Self-repairing digital systems have recently emerged as the most promising alternative for fault-tolerant systems. However, such systems are still impractical in many cases, particularly due to the complex rerouting process that follows cell replacement. They lose efficiency when the circuit size increases, due to the extra hardware in addition to the functional circuit and the unutilization of normal operating hardware for fault recovery. In this paper, we propose a system inspired by endocrine cellular communication, which simplifies the rerouting process in two ways: 1) by lowering the hardware overhead along with the increasing size of the circuit and 2) by reducing the hardware unutilized for fault recovery while maintaining good fault-coverage. The proposed system is composed of a structural layer and a gene-control layer. The structural layer consists of novel modules and their interconnections. In each module of our system, the encoded data, called the genome, contains information about the function and the connection. Therefore, a faulty module can be replaced and the whole system's functions and connections are maintained by simply assigning the same encoded data to a spare (stem) module. In existing systems, a huge amount of hardware, such as a dynamic routing system, is required for such an operation. The gene-control layer determines the neighboring spare module in the structural layer to replace the faulty module without collision. We verified the proposed mechanism by implementing the system with a field-programmable gate array with the application of a digital clock whose status can be monitored with light-emitting-diodes. In comparison with existing methods, the proposed architecture and mechanism are efficient enough for application with real fault-tolerant systems dealing with harsh and remote environments, such as outer space or deep sea.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2013-06
Language
English
Article Type
Article
Keywords

DEFECT-TOLERANT; ARCHITECTURE; EMBRYONICS; CIRCUITS; MATRIX; ARRAYS; DESIGN

Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.21, no.6, pp.1027 - 1040

ISSN
1063-8210
DOI
10.1109/TVLSI.2012.2203618
URI
http://hdl.handle.net/10203/255007
Appears in Collection
BiS-Journal Papers(저널논문)
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