DC Field | Value | Language |
---|---|---|
dc.contributor.author | Baek, Seung-Yeob | ko |
dc.contributor.author | Lee, Jae-Kyum | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2019-04-15T14:52:40Z | - |
dc.date.available | 2019-04-15T14:52:40Z | - |
dc.date.created | 2013-10-22 | - |
dc.date.issued | 2013-09 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.60, no.9, pp.562 - 566 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | http://hdl.handle.net/10203/254489 | - |
dc.description.abstract | A 12-bit 3-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) was implemented with a modified addition-only digital error correction (ADEC) and a dual-register-based DAC control as speed-enhancement techniques. The proposed speed-enhanced ADEC (SE-ADEC) scheme employs designated capacitors for redundancy-related DAC operation and thus eliminates MUX stages from the DAC control logic. Further speed enhancement is achieved by the dual-register structure that eliminates the entire DAC switching logic. The prototype ADC was fabricated in a 0.35-mu m CMOS process utilizing only thick gate transistors with a minimum gate length of 0.5 mu m. With a highly linear capacitor DAC design, the prototype ADC achieves 0.38 LSB INL without calibration. The measured spurious-free dynamic range and signal-to-noise and distortion ratio (SNDR) at a low-frequency operation of 250 kS/s are 88 and 68 dB, respectively. At a sample rate of 3 MS/s, the ADC achieves a peak SNDR of 64 dB with a total power dissipation of 1.23 mW under a 2.3-V supply. The FOMNyq is a 368-fJ/conversion-step. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers | - |
dc.type | Article | - |
dc.identifier.wosid | 000324651800006 | - |
dc.identifier.scopusid | 2-s2.0-84884588008 | - |
dc.type.rims | ART | - |
dc.citation.volume | 60 | - |
dc.citation.issue | 9 | - |
dc.citation.beginningpage | 562 | - |
dc.citation.endingpage | 566 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.identifier.doi | 10.1109/TCSII.2013.2268434 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.contributor.nonIdAuthor | Baek, Seung-Yeob | - |
dc.contributor.nonIdAuthor | Lee, Jae-Kyum | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Addition-only digital error correction (ADEC) | - |
dc.subject.keywordAuthor | digital error correction | - |
dc.subject.keywordAuthor | successive approximation register (SAR) ADC | - |
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