A 6.5-mu W/MHz Charge Buffer With 7-fF Input Capacitance in 65-nm CMOS for Noncontact Electropotential Sensing

Abstract

This brief presents a CMOS charge buffer with femtofarad-range input capacitance for applications in capacitive electropotential sensing. We analyze and verify a feedback mechanism to negate parasitic capacitances seen at the input of a CMOS amplifier. Measurements are presented from a prototype fabricated in 65-nm CMOS occupying an active area of 193 mu m(2) with an efficiency of 6.5 mu W/MHz. Over-the-air measurements validate its applicability to electropotential sensing.