A 6.5-mu W/MHz Charge Buffer With 7-fF Input Capacitance in 65-nm CMOS for Noncontact Electropotential Sensing

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This brief presents a CMOS charge buffer with femtofarad-range input capacitance for applications in capacitive electropotential sensing. We analyze and verify a feedback mechanism to negate parasitic capacitances seen at the input of a CMOS amplifier. Measurements are presented from a prototype fabricated in 65-nm CMOS occupying an active area of 193 mu m(2) with an efficiency of 6.5 mu W/MHz. Over-the-air measurements validate its applicability to electropotential sensing.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2016-12
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.12, pp.1161 - 1165

ISSN
1549-7747
DOI
10.1109/TCSII.2016.2623591
URI
http://hdl.handle.net/10203/251905
Appears in Collection
BiS-Journal Papers(저널논문)
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