A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control

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In this brief, a 0.9-V 12-Gb/s quarter-rate two finite impulse response tap direct decision feedback equalizer (DFE) is presented. For a high-speed incorporated operation of both DFE summing and slicing, a common-mode-controlled charge-based latch (CMCCBL) is proposed. In a CMCCBL-based DFE, the common mode of the first tap feedback signal is changed to adjust the first tap feedback weight. Therefore, CMCCBL does not need the conventional first tap weighting transistors which increase the DFE feedback delay. The DFE core compensates for the FR4 printed circuit board channel loss of -22 dB at 6 GHz and consumes 4.16 mW achieving 0.347 pJ/bit for PRBS7 input. The active area of DFE is 0.0036 mm(2) in a 65-nm CMOS process.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2019-03
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.27, no.3, pp.724 - 728

ISSN
1063-8210
DOI
10.1109/TVLSI.2018.2882606
URI
http://hdl.handle.net/10203/251775
Appears in Collection
EE-Journal Papers(저널논문)
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