This brief presents a digital phase modulator for wideband polar transmitters. It adopts a digital-to-time converter (DTC) and a highly linear phase calibration loop that improves phase resolution for high data-rate systems. The proposed 10-bit DTC consists of a coarse 5-bit cascaded delay line and a fine 5-bit digitally controlled delay line. This DTC achieves a fine delay resolution with digitally controlled varactors and is capable of introducing incremental delays as small as 2.49 ps. A phase calibration loop based on an advanced successive approximation register (SAR) time-to-digital converter (TDC) is nested inside the phase modulator and sets the DTC output phase accurately across the range of input digital codes. The SAR TDC also compensates for any process, voltage, and temperature variations. By using the proposed SAR TDC-based calibration loop, the phase modulator can achieve a high sampling rate and a fine phase resolution. This was possible because the number of phase comparisons of the SAR TDC has been significantly reduced. The phase modulator achieves 0.61 degrees root-mean-square phase error and a 30 MS/s sampling rate at the carrier frequency of 600 MHz while consuming 9.4 mW. This phase modulator is implemented in a 180-nm CMOS technology and occupies 0.19 mm(2).