Showing results 1 to 5 of 5
A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU Hong, Seokin; Kim, Soontae, IEEE TRANSACTIONS ON COMPUTERS, v.64, no.9, pp.2433 - 2446, 2015-09 |
CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems Kim, Jinkwon; Hong, Seokin; Hong, Jeongkyu; Kim, Soontae, IEEE TRANSACTIONS ON COMPUTERS, v.70, no.7, pp.1132 - 1145, 2021-07 |
Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures Hong, Seokin; Kim, Soontae, IEEE TRANSACTIONS ON COMPUTERS, v.65, no.10, pp.2999 - 3012, 2016-10 |
Ensuring Cache Reliability and Energy Scaling at Near-Threshold Voltage With Macho Mahmood, Tayyeb; Hong, Seokin; Kim, Soon-Tae, IEEE TRANSACTIONS ON COMPUTERS, v.64, no.6, pp.1694 - 1706, 2015-06 |
Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages Lee, Wonyoung; Kang, Mincheol; Hong, Seokin; Kim, Soontae, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.27, no.9, pp.2033 - 2045, 2019-09 |
Discover