Showing results 3 to 5 of 5
Instruction scheduling for low power Parikh, A; Kim, Soontae; Kandemir, M; Vijaykrishnan, N; Irwin, MJ, JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, v.37, no.1, pp.129 - 149, 2004-05 |
Optimizing leakage energy consumption in cache bitlines Kim, Soontae; Vijaykrishnan, N; Kandemir, M; Irwin, MJ, DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, v.9, no.1, pp.5 - 18, 2004 |
Reducing non-deterministic loads in low-power caches via early cache set resolution Kim, Soontae; Vijaykrishnan, N; Irwin, MJ, MICROPROCESSORS AND MICROSYSTEMS, v.31, no.5, pp.293 - 301, 2007-08 |
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