DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kang, Sanghoon | ko |
dc.contributor.author | Lee, Jinmook | ko |
dc.contributor.author | Lee, Jinsu | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2019-01-22T08:16:20Z | - |
dc.date.available | 2019-01-22T08:16:20Z | - |
dc.date.created | 2018-12-19 | - |
dc.date.created | 2018-12-19 | - |
dc.date.created | 2018-12-19 | - |
dc.date.issued | 2017-05 | - |
dc.identifier.citation | IEEE International Symposium on Circuits and Systems (ISCAS), pp.1902 - 1905 | - |
dc.identifier.issn | 0271-4302 | - |
dc.identifier.uri | http://hdl.handle.net/10203/248954 | - |
dc.description.abstract | An ultra-low-power face frontalization processor (FFP) is proposed for accurate face recognition in wearable devices. 3D face frontalization is essential in face recognition to guarantee human-level accuracy even with rotated or tilted faces. To reduce external memory access (EMA), which causes large power consumption, regression weight quantization with K-means clustering is proposed with the result of 81.25% EMA reduction. In addition, pipelined memory-level zero-skipping regression reduces the EMA by additional 98.43% without latency overhead. Moreover, for low-power consumption of accelerating heterogeneous workload, energy-efficient shared PE array architecture is proposed. While accelerating computation intensive process by allocating large number of PEs for utilizing data-level parallelism, unused PEs are clock-gated for preventing needless power consumption during computationally light process. Proposed workload adaptation with clock-gating showed 37.14% power reduction. The proposed FFP was implemented in 65nm CMOS process, and showed 0.53mW power consumption with 4.73fps throughput, both of which satisfy condition for always-on face recognition in wearable devices. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.title | A 0.53mW Ultra-Low-Power 3D Face Frontalization Processor for Face Recognition with Human-Level Accuracy in Wearable Devices | - |
dc.type | Conference | - |
dc.identifier.wosid | 000439261800004 | - |
dc.identifier.scopusid | 2-s2.0-85032693528 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 1902 | - |
dc.citation.endingpage | 1905 | - |
dc.citation.publicationname | IEEE International Symposium on Circuits and Systems (ISCAS) | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | Baltimore Marriott Waterfront | - |
dc.identifier.doi | 10.1109/ISCAS.2017.8050764 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.