A Hybrid Dual-Path Step-Down Converter with 96.2% Peak Efficiency Using a μ Large-DCR Inductor
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Cho, Gyu-Hyeong | ko |
| dc.contributor.author | Yeunhee, Huh | ko |
| dc.date.accessioned | 2019-01-22T08:11:42Z | - |
| dc.date.available | 2019-01-22T08:11:42Z | - |
| dc.date.created | 2018-12-26 | - |
| dc.date.created | 2018-12-26 | - |
| dc.date.issued | 2018-06-22 | - |
| dc.identifier.citation | 2018 IEEE Symposium on VLSI Circuits | - |
| dc.identifier.uri | http://hdl.handle.net/10203/248892 | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | A Hybrid Dual-Path Step-Down Converter with 96.2% Peak Efficiency Using a μ Large-DCR Inductor | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000853983300089 | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | 2018 IEEE Symposium on VLSI Circuits | - |
| dc.identifier.conferencecountry | US | - |
| dc.identifier.conferencelocation | Hilton Hawaiian Village, Honolulu, HI | - |
| dc.contributor.localauthor | Cho, Gyu-Hyeong | - |
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