Design and Analysis of Interposer-level Integrated Voltage Regulator for Power Noise Suppression in High Bandwidth Memory I/O Interface

Abstract

In this paper, we propose an interposer-level integrated voltage regulator (IIVR) scheme to suppress the power noise in next-generation high bandwidth memory (HBM) input and output (I/O) interface. The proposed IIVR is a CMOS switching voltage regulator consisting of active circuits and inductors fabricated on an active interposer and a package substrate respectively. To verify the proposed IIVR, it is analyzed by time and frequency domain simulations. The proposed IIVR can suppress internal simultaneous switching noise and isolate external broadband power noise. We have verified that the proposed IIVR successfully enables the 4 Gbps signal transfer of the next generation HBM.