DC Field | Value | Language |
---|---|---|
dc.contributor.author | Seo, Min-Jae | ko |
dc.contributor.author | Roh, Yi-Ju | ko |
dc.contributor.author | Chang, Dong-Jin | ko |
dc.contributor.author | Kim, Wan | ko |
dc.contributor.author | Kim, Ye-Dam | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2018-12-20T06:49:29Z | - |
dc.date.available | 2018-12-20T06:49:29Z | - |
dc.date.created | 2018-12-10 | - |
dc.date.created | 2018-12-10 | - |
dc.date.created | 2018-12-10 | - |
dc.date.issued | 2018-12 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.12, pp.1904 - 1908 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | http://hdl.handle.net/10203/248247 | - |
dc.description.abstract | This brief proposes a code-reusable design methodology for synthesizable successive approximation register (SAR) ADCs based on the digital design flow to significantly reduce design effort. The SAR ADCs are composed of a capacitor-DAC (CDAC) macro cell generated by a CDAC compiler and analog functional blocks implemented utilizing digital standard cells. Two prototypes of SAR ADCs (12-bit 100 kS/s and 11-bit 50 MS/s) are fabricated in different CMOS processes (180 nm and 28 nm). The prototype ADCs prove the effectiveness of the proposed design methodology with comparable performances with full-custom designed SAR ADCs. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks | - |
dc.type | Article | - |
dc.identifier.wosid | 000451260100019 | - |
dc.identifier.scopusid | 2-s2.0-85057398922 | - |
dc.type.rims | ART | - |
dc.citation.volume | 65 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 1904 | - |
dc.citation.endingpage | 1908 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.identifier.doi | 10.1109/TCSII.2018.2822811 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Design methodology | - |
dc.subject.keywordAuthor | successive approximation register (SAR) ADC | - |
dc.subject.keywordAuthor | capacitor-DAC (CDAC) compiler | - |
dc.subject.keywordAuthor | analog circuit synthesis | - |
dc.subject.keywordAuthor | skewed NAND-based comparator | - |
dc.subject.keywordAuthor | synthesizable bootstrapped switch | - |
dc.subject.keywordAuthor | standard cell | - |
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