A 22.8-to-32.4 GHz Injection-locked Frequency Tripler with Source Degeneration

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In this paper, injection-locked frequency tripler with wide locking range and high fundamental tone rejection is presented. Undesired fundamental harmonic due to the injected signal is notched out with the source degeneration. Prototype circuit is designed in 45-nm CMOS technology and achieves 28.4 dBc of harmonic rejection ratio. The tripler exhibits 34.8% of locking range with 4 dBm of input signal power. With 1.1 V of supply voltage, the core circuit consumes 5.2 mA and occupies only 265μm x 160μm of chip-area.
Publisher
ISOCC
Issue Date
2018-11-14
Language
English
Citation

15th International SoC Design Conference(ISOCC), pp.107 - 108

DOI
10.1109/ISOCC.2018.8649927
URI
http://hdl.handle.net/10203/247265
Appears in Collection
EE-Conference Papers(학술회의논문)
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