In this paper an efficient structure to compute syndromes is proposed for Reed-Solomon decoders. The proposed method formulates all the computations relevant to syndromes as a matrix multiplication so as to enlarge the search area for common sub-expressions. In contrast to the conventional architecture, the proposed method completely removes finite-field adders as they are embedded in the single matrix multiplication. The hardware resources are drastically reduced by sharing common sub-expressions and eliminating finite-field adders. Syndrome calculation blocks for various RS codes are synthesized with a 0.13 mu m CMOS technology, and experimental results show that the proposed method reduces the hardware complexity of parallel syndrome calculation by approximately 50% compared to the conventional structure.