DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kang, Hyun-Wook | ko |
dc.contributor.author | Hong, Hyeok-Ki | ko |
dc.contributor.author | Kim, Wan | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2018-10-19T00:30:07Z | - |
dc.date.available | 2018-10-19T00:30:07Z | - |
dc.date.created | 2018-09-27 | - |
dc.date.created | 2018-09-27 | - |
dc.date.created | 2018-09-27 | - |
dc.date.issued | 2018-09 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.9, pp.2584 - 2594 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/245891 | - |
dc.description.abstract | This paper presents a two-way time-interleaved (TI) 12-b 270-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a virtual-timing-reference timing-skew calibration scheme, in which the timing-skew calibration spurs present in conventional calibration schemes are effectively suppressed with the deferred reference sampling edge. The proposed design runs in a true background mode of operation, whose accuracy is independent of the statistics and the wide-sense stationary property of the input. A 12-b 270-MS/s prototype ADC with the on-chip timing-skew and offset calibration circuits is fabricated in a 40-nm CMOS process, where the timing-skew calibration circuits occupy only 9.7% of the total core area, showing the simplicity and ease of integration of the calibration algorithm even in large-scale TI ADCs. The prototype achieves a peak SNDR of 60.2 dB and a Nyquist-rate SNDR of 59.7 dB while consuming 4.5 mW from a 0.9-V supply, which then results in a Walden FoM of 21.1 fJ/conversion-step. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | NM CMOS | - |
dc.title | A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme | - |
dc.type | Article | - |
dc.identifier.wosid | 000444279300013 | - |
dc.identifier.scopusid | 2-s2.0-85048851914 | - |
dc.type.rims | ART | - |
dc.citation.volume | 53 | - |
dc.citation.issue | 9 | - |
dc.citation.beginningpage | 2584 | - |
dc.citation.endingpage | 2594 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2018.2843360 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Calibration | - |
dc.subject.keywordAuthor | delay control | - |
dc.subject.keywordAuthor | time-interleaved (TI) analog-to-digital converter (ADC) | - |
dc.subject.keywordAuthor | timing-skew | - |
dc.subject.keywordAuthor | virtual-timing-reference (VTR) | - |
dc.subject.keywordPlus | NM CMOS | - |
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