A 230-260GHz wideband amplifier in 65nm CMOS based on dual-peak Gmax-core

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dc.contributor.authorPark, Dae-Woongko
dc.contributor.authorDzuhri Radityo Utomoko
dc.contributor.authorHong, Jong-Philko
dc.contributor.authorLee, Sang-Gugko
dc.date.accessioned2018-07-24T02:32:11Z-
dc.date.available2018-07-24T02:32:11Z-
dc.date.created2018-06-08-
dc.date.created2018-06-08-
dc.date.created2018-06-08-
dc.date.created2018-06-08-
dc.date.created2018-06-08-
dc.date.issued2018-01-
dc.identifier.citation23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp.301 - 302-
dc.identifier.issn2153-671X-
dc.identifier.urihttp://hdl.handle.net/10203/244200-
dc.description.abstractA dual-peak maximum achievable gain core design technique is proposed. It has been adopted into a 4-stage wideband amplifier. Implemented in a 65nm CMOS, the amplifier achieves 3dB bandwidth of 30GHz (230 similar to 260GHz), gain of 12.4 +/- 1.5dB, and peak PAE of 1.6% while dissipating 23.8mW, which corresponds to the widest bandwidth and highest gain per stage among other reported CMOS amplifiers operating above 200GHz.-
dc.languageEnglish-
dc.publisherIEEE-
dc.titleA 230-260GHz wideband amplifier in 65nm CMOS based on dual-peak Gmax-core-
dc.typeConference-
dc.identifier.wosid000428759000114-
dc.identifier.scopusid2-s2.0-85034038719-
dc.type.rimsCONF-
dc.citation.beginningpage301-
dc.citation.endingpage302-
dc.citation.publicationname23rd Asia and South Pacific Design Automation Conference (ASP-DAC)-
dc.identifier.conferencecountryKO-
dc.identifier.conferencelocationInternational Convention Center Jeju-
dc.identifier.doi10.1109/ASPDAC.2018.8297330-
dc.contributor.localauthorLee, Sang-Gug-
dc.contributor.nonIdAuthorPark, Dae-Woong-
dc.contributor.nonIdAuthorDzuhri Radityo Utomo-
dc.contributor.nonIdAuthorHong, Jong-Phil-
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EE-Conference Papers(학술회의논문)
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