Application specific DRAM address mapping

Abstract

The initial location of data in DRAMs is fixed and controlled by the ‘address-mapping’. Whereas, the memory access pattern can change dynamically which means that we cannot extract DRAM performance efficiently. Recently, Dynamic Re-arrangement of Address Mapping (DReAM) found out a way to detect application specific address mapping by finding and assigning the bits which have highest change rate to column, bank, rank and channel bits to reduce the bank conflicts. However, this scheme results in a lot of bit re-assignment. We found out that this much of bit re-assignment is not necessary and assigning bits based on the application’s memory access features like row buffer hit rate, no. of concurrent streams can give a better performance and energy efficiency. The scheme presented in this thesis gives 12% IPC improvement as compared to baseline and up to 51% in single core experiments. It reduces energy consumption up to 15% on average. Row buffer hit rate has also improved significantly and activation precharge energy is reduced 33% on average. Our scheme also outperforms the DReAM’s scheme in nearly all of the above presented metrics. For multi core experiments, it shows performance improvement of 2.7% on average and energy efficiency of 9% across all workloads.